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1 document # sram113 rev a revised october 2005 p4c198/p4c198l, p4c198a/p4c198al ultra high speed 16k x 4 static cmos rams features full cmos, 6t cell high speed (equal access and cycle times) ? 10/12/15/20/25 ns (commercial) ? 12/15/20/25/35 ns (industrial) ? 15/20/25/35/45 ns (military) low power operation (commercial/military) 5v 10% power supply data retention, 10 a typical current from 2.0v p4c198l/198al (military) output enable & chip enable control functions ? single chip enable p4c198 ? dual chip enable p4c198a common inputs and outputs fully ttl compatible inputs and outputs standard pinout (jedec approved) ? 24-pin 300 mil dip ? 24-pin 300 mil soj ? 28-pin 350 x 550 mil lcc functional block diagram pin configurations the p4c198/l and p4c198a/l are 65,536-bit ultra high- speed static rams organized as 16k x 4. each device features an active low output enable control to eliminate data bus contention. the p4c198/l also have an active low chip enable (the p4c198a/l have two chip enables, both active low) for easy system expansion. the cmos memories require no clocks or refreshing and have equal access and cycle times. inputs are fully ttl-compatible. the rams operate from a single 5v 10% tolerance power supply. data integrity is maintained with supply description voltages down to 2.0v. current drain is typically 10 a from a 2.0v supply. access times as fast as 12 nanoseconds are available, permitting greatly enhanced system operating speeds. cmos is used to reduce power consumption to a low 715 mw active, 193 mw standby. the p4c198/l and p4c198a/l are available in 24-pin 300 mil dip and soj, and 28-pin 350 x 550 mil lcc packages providing excellent board level densities. dip (p4, c4, d4), soj (j4) p4c198 (p4c198a) lcc (l5) p4c198 (p4c198a)
p4c198/198l, p4c198a/198al page 2 of 13 document # sram113 rev a ce 1 , ce 2 v ih mil. v cc = max., ind./com?l. f = 0, outputs open v in v lc or v in v hc maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +7 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum ratingconditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. recommended operating temperature and supply voltage i sb standby power supply current (ttl input levels) ce 1 , ce 2 v ih mil. v cc = max ., ind./com?l. f = max., outputs open ___ ___ 40 35 ___ ___ ___ ___ 20 15 40 n/a 1.5 n/a ma ma ___ ___ standby power supply current (cmos input levels) i sb1 commercial grade(2) ambient temperature gnd v cc 0c to +70c ?40c to +85c 0v 0v 5.0v 10% 5.0v 10% 0v 5.0v 10% ?55c to +125c military symbol c in c out parameter input capacitance output capacitance conditions v in = 0v v out = 0v 5 7 unit pf pf capacitances (4) v cc = 5.0v, t a = 25c, f = 1.0mhz n/a = not applicable symbol dc electrical characteristics over recommended operating temperature and supply voltage (2) v ih v il v hc v lc v cd v ol v oh i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input clamp diode voltage output low voltage (ttl load) output high voltage (ttl load) input leakage current output leakage current test conditions v cc = min., i in = ?18 ma i ol = +10 ma, v cc = min. i ol = +8 ma, v cc = min. i oh = ?4 ma, v cc = min. v cc = max. mil. v in = gnd to v cc ind./com?l. v cc = max., ce = v ih , mil. v out = gnd to v cc ind./com?l. p4c198 / 198a min 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?10 ?5 ?10 ?5 max v cc +0.5 0.8 v cc +0.5 0.2 ?1.2 0.4 +10 +5 +10 +5 p4c198l / 198al min max 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?5 n/a ?5 n/a v cc +0.5 0.8 v cc +0.5 0.2 0.4 ?1.2 +5 n/a +5 n/a unit v v v v v v v v a a typ. industrial 0.5 0.5
p4c198/198l, p4c198a/198al page 3 of 13 document # sram113 rev a data retention characteristics (p4c198l/p4c198al military temperature only) typ.* max symbol parameter test condition min v cc =v cc = unit 2.0v 3.0v 2.0v 3.0v v dr v cc for data retention 2.0 v i ccdr data retention current 10 15 600 900 a t cdr chip deselect to ce v cc ? 0.2v, 0 ns data retention time v in v cc ? 0.2v or t r ? operation recovery time t rc ns * t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested. *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. 198: ce = v il , oe = v ih 198a: ce 1 = v il , ce 2 = v il . oe = v ih v in 0.2v data retention waveform i cc symbol parameter temperature range dynamic operating current* commercial industrial military ?10 n/a ?12 ?15 ?20 ?25 ?35 ?45 unit n/a ma ma ma power dissipation characteristics vs. speed n/a 150 155 160 170 180 n/a 170 160 155 150 145 180 170 160 155 150 n/a n/a
p4c198/198l, p4c198a/198al page 4 of 13 document # sram113 rev a sym. parameter unit -10 -12 -15 -20 -25 -35 -45 min max min max min max min max min max min max min max t rc read cycle time 10 12 15 20 25 35 45 ns t aa address access 10 12 15 20 25 35 45 ns time t ac chip enable 10 12 15 20 25 35 45 ns access time t oh output hold from 2 2 2222 2ns address change t lz chip enable to 2 2 2222 2ns output in low z t hz chip disable to 6 7 8 10 10 14 15 ns output in high z t oe output enable 6 7 9 12 15 25 30 ns low to data valid t olz output enable to 2 2 2222 2ns output in low z t ohz output disable to 6 7 9 9 10 14 15 ns output in high z t pu chip enable to 0 0 0000 0ns power up time t pd chip disable to 10 12 15 20 25 35 45 ns power down time ac characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) read cycle no.1 ( oe oe oe oe oe controlled) (5) notes: 5. we is high for read cycle.
p4c198/198l, p4c198a/198al page 5 of 13 document # sram113 rev a read cycle no. 2 (address controlled) (5,6) read cycle no. 3 ( ce ce ce ce ce (12) controlled) (5,7,8) 10. read cycle time is measured from the last valid address to the first transitioning address. 11. transitions caused by a chip enable control have similar delays irrespective of whether ce 1 or ce 2 causes them (p4c198a/l). 12. ce 1 , ce 2 for p4c198a/l. notes: 6. ce ( ce 1 ce 2 for p4c198a/l) and oe are low read cycle. 7. oe is low for the cycle. 8. address must be valid prior to, or coincident with ce ( ce 1 and ce 2 for p4c198a/l) transition low. 9. transition is measured 200mv from steady state voltage prior to change, with loading as specified in figure 1.
p4c198/198l, p4c198a/198al page 6 of 13 document # sram113 rev a -10 -12 -15 -20 -25 -35 -45 min max min max min max min max min max min max min max t wc write cycle time 10 12 13 15 20 30 40 ns t cw chip enable time 7 8 10 15 20 30 35 ns to end of write t aw address valid to 8 8 10 15 20 25 35 ns end of write t as address set-up 0 0 00000ns time t wp write pulse 8 9 10 12 20 25 35 ns width t ah address hold 0 0 00000ns time from end of write t dw data valid to end 7 6 7 10 13 15 20 ns of write t dh data hold time 0 0 00000ns t wz write enable to 7 6 7 8 10 10 15 ns output in high z t ow output active 3 3 33333ns from end of write ac characteristics?write cycle (v cc = 5v 10%, all temperature ranges) (2) sym. parameter unit write cycle no. 1 (with oe oe oe oe oe high)
p4c198/198l, p4c198a/198al page 7 of 13 document # sram113 rev a write cycle no. 2 ( we we we we we controlled) (13,14) 1520 08 write cycle no. 3 ( ce ce ce ce ce (12) controlled) (13,14) notes: 13. ce ( ce 1 , ce 2 for p4c198a/l) and we must be low for write cycle. 14. oe is low for this write cycle. 15. if ce ( ce 1 or ce 2 for p4c198a/l) goes high simultaneously with we high, the output remains in a high impedance state. 16. write cycle time is measured from the last valid address to the first transitioning address.
p4c198/198l, p4c198a/198al page 8 of 13 document # sram113 rev a truth tables p4c198/l p4c198a/l ce ce ce ce ce 1 ce ce ce ce ce 2 we we we we we oe oe oe oe oe mode output h x x x standby high z x h x x standby high z l l h h output inhibit high z l l h l read d out l l l x write d in ce ce ce ce ce we we we we we oe oe oe oe oe mode output h x x standby high z l h h output inhibit high z l h l read d out l l x write d in input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 * including scope and test fixture. note: because of the ultra-high speed of the p4c198/l and p4c198a/l, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high figure 1. output load figure 2. thevenin equivalent frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance). ac test conditions
p4c198/198l, p4c198a/198al page 9 of 13 document # sram113 rev a * military temperature range with mil-std-883, class b processing. n/a = not available selection guide the p4c198 and p4c198a are available in the following temperature, speed and package options. ordering information 10 12 15 20 25 35 45 plastic dip -10pc -12pc -15pc -20pc -25pc n/a n/a plastic soj -10jc -12jc -15jc -20jc -25jc n/a n/a industrial plastic dip n/a -12pi -15pi -20pi -25pi -35pi n/a plastic soj n/a -12ji -15ji -20ji -25ji -35ji n/a side brazed dip n/a n/a -15cm -20cm -25cm -35cm -45cm cerdip n/a n/a -15dm -20dm -25dm -35dm -45dm lcc n/a n/a -15lm -20lm -25lm -35lm -45lm side brazed dip n/a n/a -15cmb -20cmb -25cmb -35cmb -45cmb cerdip n/a n/a -15dmb -20dmb -25dmb -35dmb -45dmb lcc n/a n/a -15lmb -20lmb -25lmb -35lmb -45lmb speed (ns) military temperature military processed* temperature range package commercial
p4c198/198l, p4c198a/198al page 10 of 13 document # sram113 rev a pkg # # pins symbol min max a-0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d-1.280 e 0.220 0.310 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 - 0.100 bsc c4 24 (300 mil) 0.300 bsc pkg # # pins symbol min max a-0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d-1.280 e 0.220 0.310 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - 0 15 0.100 bsc d4 24 (300 mil) 0.300 bsc side brazed dual in-line package cerdip dual in-line package
p4c198/198l, p4c198a/198al page 11 of 13 document # sram113 rev a pkg # # pins symbol min max a 0.128 0.148 a1 0.082 - b 0.016 0.020 c 0.007 0.010 d 0.620 0.630 e e e1 0.292 0.300 e2 q0.025- j4 24 (300 mil) 0.050 bsc 0.267 bsc 0.335 bsc pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.342 0.358 d1 d2 d3 - 0.358 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne 0.020 ref 5 9 0.400 bsc 0.200 bsc 0.050 bsc 0.040 ref l5 28 0.200 bsc 0.100 bsc soj small outline ic package rectangular leadless chip carrier
p4c198/198l, p4c198a/198al page 12 of 13 document # sram113 rev a pkg # # pins symbol min max a-0.210 a1 0.015 - b 0.014 0.022 b2 0.045 0.070 c 0.008 0.014 d 1.230 1.280 e1 0.240 0.280 e 0.300 0.325 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p4 24 (300 mil) plastic dual in-line package
p4c198/198l, p4c198a/198al page 13 of 13 document # sram113 rev a revisions document number : sram113 document title : p4c198 / p4c198l, p4c198a / p4c198al ultra high speed 16k x 4 static cmos rams rev. issue date orig. of change description of change or 1997 dab new data sheet a oct-05 jdb change logo to pyramid

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